The increasing consumer demand for new and cheaper electronic devices continues to drive the semiconductor industry to decrease product life cycles and reduce costs. As a result, programmable logic devices (PLDs) are becoming the preferred building blocks over application-specific integrated circuits (ASICs) because of their flexibility during the early development stage of a product, allowing for rapid development at low cost.
Programmable logic devices (PLDs), including complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs), are a class of integrated circuits that can be programmed and reprogrammed by the user to implement different logic functions, unlike customized hard-wired chips or ASICs that have set functionality. FPGA and CPLD integrated circuits typically contain an array of internal configurable logic blocks, programmable interconnects and switches, and a periphery of input/output (I/O) blocks. The logic blocks and interconnecting elements are programmed to realize the desired function. The I/O blocks are coupled to I/O pins used to supply power and transport logic signals to and from the logic blocks.
Programmability of a PLD is provided through fuses which are stored in a memory array that may be located on or off chip. Fuses stored off-chip are stored in a memory chip containing non-volatile memory and logic control circuits, such as standard memory or a configurator chip. When power is initially supplied to the PLD, the fuses are downloaded and stored on the PLD. These fuses are lost as soon as the power is cutoff. Fuses stored permanently on-chip are stored in a non-volatile memory array in the PLD and therefore are not lost in the absence of power. Supplying power to the PLD loads some or all of the fuses from the memory array into latches. If only some of the fuses are loaded into latches, the other fuses are read directly from the non-volatile memory array. In this case, a sense amplifier may be used in order to speed up the read-out rate from non-volatile memory. A drawback of using a sense amplifier is that it drains current. Alternatively, the fuses can be loaded externally through the aid of a microcontroller. An externally loaded process may provide greater freedom to update the fuses whenever needed. It also avoids the time-consuming program sequence performed to non-volatile memory both on and off chip.
In addition to the programmability support described above, PLDs may support advanced input/output (I/O) standards such as High-Speed Transceiver Logic (HSTL) classes I, II, III, Stub Series Terminated Logic-3 (SSTL-3) classes I, II, SSTL-2 classes I, II, SSTL-18 classes I, II and others. In order to meet all these single-ended signal standards, a comparator and a reference voltage are preferably provided such that the comparator compares an input signal to the reference voltage to determine whether the input is logic “1” or logic “0”. A comparator is preferably located inside each of the I/O blocks and the reference voltage is preferably provided from outside the chip. Purely by way of example, the EIA/JESD8-9 SSTL-2 input standard is provided in Table 1 (shown in the Appendix). The SSTL-2 operating voltage 2.5V±0.2V, and the reference voltage VREF ranges from 1.13V to 1.32V.
For the purpose of higher system integration on a mixed signal platform, it is desirable to implement an analog-to-digital converter (ADC) within PLD circuits that are configured to support advanced I/O standards and accordingly include comparators. Prior art implementations of ADCs in PLDs are inefficient because they include excess circuitry, such as a second I/O pad in each I/O block, and waste space and sacrifice accuracy by spreading resistors over a plurality of I/O blocks. The prior art also lacks the flexibility to adjust the resolution of an ADC result. Additionally, the prior art does not offer the ability to safeguard against current leaks across the resistors, and does not permit the use of digital input and output paths of the I/O blocks when the I/O blocks are being used as part of the ADC. Hence, there exists a need for implementing ADCs within PLDs without the limitations of the prior art.